Lab 4 - ECE 421L
IV Characteristics and Layout of NMOS and PMOS DEVICES
First, we were instructed to backup our work which is shown below:
After reading through the lab we were instructed to complete Tutorial 2. It starts with us creating a schematic and symbol of an NMOS:
Then we had to create a circuit using our symbol:
With this circuit, we ran a parametric anaysis on it:
After that, we made a layout for our NMOS:
With the layout, we performed an LVS where the netlists matched, then we ran a parametric analysis with the extracted:
Next we created the schematic and symbol for a PMOS:
After that, we created a circuit using our symbol:
Then we run a parametric analysis on our circuit:
Then we make our PMOS layout:
After we extract and LVS, we run our parametric analysis again with the extraced:
Lab:
-A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio:
-A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio.
-A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio.
-A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.
-Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads and directly adjacent to the MOSFET (so the layout is relative small).
First, we make our layout of our probe pad, then create the schematic for it and a symbol:
Next, we create a circuit for an nmos using the probe pab symbol:
Then, we create a layout of the NMOS with the probe pads, which we DRC.
After we have no DRC errors, we extrace the layout then put it through LVS:
After we have our netlist's match, we run the parametric analysis with the extracted view:
-Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads.
Next, we repeat the process, but with a PMOS, first creating the circuit with the probe pads:
Then, creating a layout and checking DRC:
Then, we extraced our layout and run it through LVS:
Once our netlists match, we run it through a parametric analysis:
Once we complete the lab, we download out data and zip in, and I backed it up on my google drive, with a google doc file with all my images:
